Technology
Inside the sensor matrix.
Every Vyanika deployment is built on the same three-layer stack: sense, decide, sync — all resolved at the edge.
Pressure-Sensing Grid
A piezoresistive sensing grid is laminated beneath the playing surface, wired into a scanning matrix that reads pressure at every intersection. Exact material is still in validation.
Edge Processing Unit
A local microcontroller reads the grid and resolves footfall position and boundary crossings without a network round-trip.
Protective Stack
The sensor layer sits beneath a protective stack designed to preserve surface feel and player experience. Full spec and wear-layer material are still in validation.
Specifications
Built for competitive play.
Sensing Layer
Design targetPiezoresistive matrix
A pressure-sensing grid laminated beneath the playing surface. Exact material is still in validation.
Matrix Density
Frozen spec256 nodes / tile
A 32×8 sensing grid per tile, scanned continuously across the covered surface.
End-to-End Latency
Design target≤50ms (P95)
Design budget from footfall to referee device. Engineering estimate is ≈43ms worst-case — not yet measured on hardware.
Boundary Resolution
Pending validation≤±1.5cm
Target spatial precision across the line. Validation testing is not yet complete.
Stack Thickness
Design target≤10mm
Total sensor and protective stack, designed to preserve surface feel and player experience.
Durability
Frozen specField-replaceable tiles
Wear risk is managed by design — replaceable tiles and pre-match auto-calibration — rather than a claimed cycle count. Long-run cycling validation has not yet run.
Decision Pipeline
From footfall to call.
- 1
Footfall
A raider crosses the line. The sensing matrix registers a pressure change at the contact point.
- 2
Local Sensing
The sensor grid around the contact zone is read and filtered on-tile.
- 3
Edge Decision
On-mat hardware resolves the call locally — no cloud round-trip required.
- 4
Device Sync
The call reaches the referee's device, the ringside tablet, and the broadcast feed together.
≤50ms Target end-to-end latency (P95) — Engineering design budget ≈43ms worst-case, ~8ms margin. Not yet measured on hardware — validation pending.